1. Field of the Invention
The present invention relates to a method of fabricating integrated microstructures of semiconductor material and, in particular, to a method of fabricating an integrated piezoresistive pressure sensor having a diaphragm of polycrystalline semiconductor material. The present invention also relates to an integrated piezoresistive pressure sensor having a diaphragm of polycrystalline semiconductor material.
2. Discussion of the Related Art
Micromachining, which is based on microelectronic fabrication techniques, provides fabrication methods for microsystems such as microsensors, microactuators and special micromechanisms. In recent years, micromachining techniques have been developed for producing integrated pressure microsensors of semiconductor material. These sensors provide numerous advantages in comparison to traditional sensors: reduced cost, high degree of performance and reliability, better signal-to-noise ratio, possibility of integration with memory circuits for producing intelligent sensors, possibility of on-line self-testing, and greater reproducibility. As such, integrated pressure microsensors are increasingly used in the automotive industry, contributing to greater safety and environmental protection with absolutely no increase in vehicle cost.
Currently marketed semiconductor pressure microsensors are typically based on three physical effects: 1) a piezoresistive effect whereby the pressure-induced inflection of a silicon diaphragm unbalances a Wheatstone bridge comprising resistors diffused in the diaphragm; 2) a capacitive effect whereby pressure induces a displacement of a diaphragm forming the movable electrode of a capacitor (thus resulting in a variation in capacitance); and 3) a resonant effect whereby the pressure inflects a diaphragm to which a resonant structure is fixed and this mechanical deformation varies the oscillation frequency of the structure. For the sensor to operate effectively, the diaphragms must be of uniform, accurately controlled thickness with no intrinsic mechanical stress. These characteristics are typically achieved by forming the microstructures by plasma or wet etching, isotropically (for profiles coincident with the crystal faces) or anisotropically (for generating profiles which are independent from the crystal orientation).
Many specialized techniques have been developed to fabricate such microstructures. One such fabrication technique employs etching solutions such as ethyldiaminapyrocatechol (EDP), whereby a structure is formed and separated from the substrate by etching the bulk silicon from the front of the wafer using what is known as the xe2x80x9cfront bulk micromachiningxe2x80x9d technique.
In the mid 80""s, xe2x80x9csurface micromachiningxe2x80x9d was proposed, whereby the sensitive element or micromechanism was formed of polycrystalline silicon, and which provides for forming suspended structures by depositing and subsequently removing sacrificial layers of different types, e.g. silicon oxide or nitride, porous silicon, aluminum, photoresist, polyimide, etc. Surface micromachined suspended structures, however, are characterized by poor flexural rigidity, and have a tendency to collapse onto the underlying layer, thus impairing thermal or mechanical isolation. A general review of surface micromachining technology (as well as bulk micromachining and the characteristics of each) is to be found, for example, in the article entitled xe2x80x9cMicromachining and ASIC Technologyxe2x80x9d by Axel M. Stoffel, in Microelectronics Journal, 25 (1994), p. 145-156.
Several industrial laboratories and research centers have produced prototype integrated microstructures using the surface micromachining technique. Details of these are to be found, for example, in the articles: xe2x80x9cNovel fully CMOS-compatible vacuum sensorxe2x80x9d, by O. Paul, H. Baltes, in Sensors and Actuators A 46-47 (1995) p. 143-146, in which a diaphragm of dielectric material is formed on a sacrificial metal layer; xe2x80x9cSurface-Micromachined Piezoresistive Pressure Sensorxe2x80x9d by T. Lisec, H. Stauch, B. Wagner, in Sensor 95 Kongressband, AO1.2, p. 21-25, in which both the sacrificial layer and the diaphragm are of polysilicon and separated by a small layer of silicon oxide; and xe2x80x9cSurface-Micromachined Microdiaphragm Pressure Sensorsxe2x80x9d by S. Sugiyama, K. Shimaoka, O. Tabata, in Sensors and Materials 4, 5 (1993), p. 265-275, in which use is made of a sacrificial polysilicon layer and a silicon nitride layer as the diaphragm.
Though they do in fact provide for better integrating the devices, the above surface micromachining techniques pose serious problems with regard to the quality of the deposited films (amorphous or polycrystalline) to form the diaphragms, stiction of the suspended structures on the silicon substrate, and packaging difficulties.
In the early 90""s, a further microstructure fabrication technique, known as xe2x80x9csilicon fusion bondingxe2x80x9d, was devised, whereby a cavity is formed in a monocrystalline silicon wafer onto which a further monocrystalline silicon wafer, in which the sensor is formed, is bonded.
A similar microstructure fabrication technique employs dedicated or nondedicated SOI (Silicon-on-Insulator) substrates.
Other highly specialized techniques, such as xe2x80x9cwafer dissolving,xe2x80x9d provide for forming silicon microstructures by means of dedicated processes which are totally incompatible with standard planar microelectronics technology. In a sense, these xe2x80x9cad hocxe2x80x9d processes simply consist of transferring onto silicon what is currently done using other materials, and only provide for fabricating the sensitive portion, so that the processing and control circuit must be formed on a separate chip.
Yet another highly specialized technique is the LIGA methodxe2x80x94a German acronym for Lithographie Galvanoformung Abformungxe2x80x94which comprises three processing steps: synchrotron x-ray lithography; galvanic deposition of metal films; and formation of plastic molds (see, for example, S.M.Sze""s xe2x80x9cSemiconductor Sensorsxe2x80x9d, John Wiley and Sons, Inc., Chapter 2, p. 75-78).
At present, diaphragms of semiconductor material (silicon) are produced using the bulk micromachining technique, which is described in detail, for example, in the articles xe2x80x9cCMOS Integrated Silicon Pressure Sensorxe2x80x9d by T. Ishihara, K. Suzuki, S. Suwazono, M. Hirata and H. Tanigawa, IEEE Journal Sol. St. Circuits, vol. Sc-22, April 1987, 151-156, and xe2x80x9cMicromachining and ASIC Technologyxe2x80x9d by A. M. Stoffel, Microelectronics Journal 25 (1994) 145-156. Bulk micromachining typically involves processing a silicon wafer on both faces to exploit the excellent mechanical properties of monocrystalline silicon. However, front-to-rear processing, and the need for particular handling of the wafers make bulk micromachining incompatible with current integrated circuit fabrication technology.
Another method, known as the electrochemical stop method using a PN junction, provides for more accurately controlling the thickness of the diaphragm and eliminating any process-induced tensile or compressive stress. The electrochemcial stop method involves forming a diaphragm in an N-type monocrystalline semiconductor layer (e.g. the epitaxial layer) on a P-type substrate. The N-type layer is masked except for a previously implanted anode contact region. The rear of the substrate is masked with a mask presenting a window aligned with the region in which the diaphragm is to be formed; a positive potential difference is applied between the N-type layer and the substrate, via the anode contact region, after which the P-type substrate is chemically etched for a few hours at a relatively low temperature (e.g. 90xc2x0 C.). The chemical etching terminates automatically at the PN junction, forming the diaphragm from the N-type layer at the removed substrate region.
FIGS. 1A, 1B and 1C illustrate typical fabrication steps for forming an absolute piezoresistive pressure microsensor using the electrochemical stop method. The initial steps are those commonly adopted in the fabrication of integrated circuits. In particular, starting from a wafer 1 of monocrystalline silicon comprising a P-type substrate 2 and an N-type epitaxial layer 3, P-type junction isolation regions 4 extending from the upper surface of wafer 1 to substrate 2 are formed in epitaxial layer 3. An integrated circuit is then formed, for example, an NPN transistor with an N+-type collector contact region 6, a P-type base region 7, and an N+-type emitter region 8, as shown in FIG. 1A. Simultaneously with the integrated circuit, the diffused resistors (only one of which, comprising a P-type resistive layer 10, is shown) and one anode region for each wafer and each diaphragm (N+-type region 11 in FIG. 1A) are formed. The resistors are preferably formed in the same implant step of base region 7 of the NPN transistor. Anode region 11 is preferably formed in the same step as one of the N-type regions of the integrated circuit (e.g. when implanting collector contact region 6 or emitter region 8). A dielectric layer 12 is then deposited, and metal contacts 13 are formed.
Thereafter, wafer 1 is masked with a front mask 15 and a rear mask 16. The front mask 15 (of silicon oxide) covers the whole of the upper surface of wafer 1 except for a window at anode region 11, and the rear mask 16 (of silicon nitride or oxide) covers the whole of the lower surface of the wafer except for the region in which the diaphragm is to be formed, as shown in FIG. 1B. The rear of the wafer is then subjected to anisotropic etching while epitaxial layer 3 is biased, via anode region 11, at a positive voltage (e.g. 5V) with respect to substrate 2. Anisotropic etching terminates automatically at epitaxial layer 3, and the portion of epitaxial layer 3 at the removed portion of substrate 2 forms the diaphragm 18.
Following removal of masks 15 and 16, wafer 1 is bonded to a sheet of glass 17 (FIG. 1C) using an anodic bonding method whereby a medium-high voltage (e.g. 500 V) is applied between wafer 1 and sheet 17 for a few hours at a temperature of 300 to 400xc2x0 C. Alternatively, wafer 1 may be bonded to the sheet of glass 17 using the glass frit bonding method, which typically requires lower temperatures. Finally, sheet 17 is fixed to container 19.
The above method presents the following drawbacks: it is incompatible with batch processing techniques, due to the electric contacts on each wafer; the rear etching of wafer 1 poses problems in terms of front-rear alignment; the thickness of wafer 1 demands prolonged etching; the scaling problems involved are such as to preclude the integration of structures smaller than a few hundred micrometers; and, once the diaphragm is formed, wafer 1 must invariably be bonded to a glass support, both for absolute and differential sensors (which require holes aligned with the diaphragm, thus posing further alignment problems).
Furthermore, the anisotropy of etching causes a reduction of the otherwise available area of wafer 1; the chemical agents used, (including, for example, potassium or sodium), may contaminate the chip, causing problems in the circuit integration; and it is very difficult to control the thickness of the active diaphragm, which causes problems with sensor reproducibility.
The above drawbacks make it difficult to integrate the method in currently used integrated circuit technology. Therefore, several pressure microsensor manufacturers have opted to form a double integrated chip: one chip contains the diaphragm microstructure, while the other provides for processing the signal. Single-chip integrated sensors also exist, but are not batch processed.
None of the above methods provides a method for fabricating low-cost sensors comparable with those of microelectronics technology, using known, highly controllable, noncritical fabrication steps, and which may be integrated with the control electronics in one chip.
It is an object of the present invention to provide microstructures of semiconductor material designed to overcome the drawbacks typically associated with current technology, as well as methods of fabricating such microstructures.
The method of the present invention provides, in one embodiment, a sacrificial buried region of insulating material formed on a monocrystalline semiconductor material substrate. A polycrystalline region for forming the sensitive element or micromechanism is formed over the sacrificial buried region, a monocrystalline region is grown elsewhere, and after the electronic components are formed, portions of the polycrystalline region are selectively removed via trenches in the polysilicon to form a suspending region in which static, kinematic or dynamic microstructures are formed.
According to one embodiment of the method of the present invention, the sacrificial buried oxide region can be formed by sequentially depositing an oxide layer and a nitride layer over the substrate, photolithographically defining a window in the nitride layer to expose a portion of the underlying oxide layer, followed by growth of a thermal oxide layer.
According to another embodiment, the sacrificial buried region can be formed by photolithographically defining a window in both the nitride and oxide layers, using the nitride as an etch mask to define a recess in the substrate, followed by growth of a thermal oxide layer in the recess.
According to another embodiment, the sacrificial buried oxide region can be formed by depositing or growing an oxide region and photolithographicaly defining a region of oxide on the substrate.
After the formation of the sacrificial buried oxide region by any of the methods previously described, a semiconductor material layer is deposited over the substrate and then selectively removed to provide a germ region for epitaxial growth over the sacrificial buried oxide region. The semiconductor material layer can be amorphous or polycrystalline silicon.
At this point in the method of the present invention, standard fabrication techniques can be used to form integrated electronic components in the first semiconductor material layer.
In order to isolate the electronic components, regions surrounding the sensitive regions are photolithographically defined, followed by etching the regions and the sacrificial buried oxide region to form a suspended area.
The present invention also provides an integrated microstructure of semiconductor material, formed in a semiconductor material layer over a substrate where the semiconductor material layer is polycrystalline and monocrystalline elsewhere. The microstructure is formed over a sacrificial buried region and also includes an opening located between the substrate and the polycrystalline region. The opening is a trench that extends between an outer surface of the semiconductor material layer and the opening. The polycrystalline region thus forms, over the opening, a suspended structure supporting integrated microsensors and micromechanisms. The suspended structure is supported by connecting and supporting portions that extend between an inner portion of the polycrystalline region in which the microstructures are formed and outer regions of the semiconductor material layer.